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1 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead soic 8-lead pdip features ? medium-voltage and standard-voltage operation ?5.0(v cc = 4.5v to 5.5v) ? 2.7 (v cc = 2.7v to 5.5v) user-selectable internal organization ? 2k: 256 x 8 or 128 x 16 ? 4k: 512 x 8 or 256 x 16 three-wire serial interface sequential read operation 2 mhz clock rate (5v) self-timed write cycle (10 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years 8-lead pdip and 8-lead jedec soic packages description the at9 3 c56a/66a provides 204 8 /4096 bits of seri a l electric a lly er a s a ble progr a m- m a ble re a d-only memory (eeprom). the eeprom is org a nized a s 12 8 /256 words of 16 bits e a ch (when the org pin is connected to vcc) a nd 256/512 words of 8 bits e a ch (when the org pin is tied to ground.) the device is optimized for use in m a ny a utomotive a pplic a tions where low-power a nd low-volt a ge oper a tions a re essenti a l. the at9 3 c56a/66a is a v a il a ble in sp a ce-s a ving 8 -le a d pdip a nd 8 -le a d jedec s oic p a ck a ges. the at9 3 c56a/66a is en a bled through the chip s elect (c s ) pin a nd a ccessed vi a a three-wire seri a l interf a ce consisting of d a t a input (di), d a t a output (do), a nd s hift clock ( s k). upon receiving a re a d instruction a t di, the a ddress is decoded a nd the d a t a is clocked out seri a lly on the d a t a output pin do. the write cycle is completely self-timed, a nd no sep a r a te er a se cycle is required before write. the write cycle is only en a bled when the p a rt is in the er a se/write en a ble st a te. when c s is brought high following the initi a tion of a write cycle, the do pin outputs the re a dy/busy st a tus of the p a rt. the at9 3 c56a/66a is a v a il a ble in 4.5v to 5.5v a nd 2.7v to 5.5v versions. table 1 . pin configur a tions pin name function c s chip s elect s k s eri a l d a t a clock di s eri a l d a t a input do s eri a l d a t a output gnd ground vcc power s upply org intern a l org a niz a tion dc don?t connect three-wire serial automotive eeproms 2k (256 x 8 or 128 x 16) 4k (512 x 8 or 256 x 16) at93c56a at93c66a preliminary 3 40 3 d? s eepr?10/04
2 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 figure 1. block di a gr a m note: when the org pin is connected to vcc, the ?x 16? org a niz a tion is selected. when it is connected to ground, the ?x 8 ? org a niz a - tion is selected. if the org pin is left unconnected a nd the a pplic a tion does not lo a d the input beyond the c a p a bility of the intern a l 1 meg ohm pullup, then the ?x 16? org a niz a tion is selected. absolute maximum ratings* oper a ting temper a ture ......................................? 55 c to +125 c *notice: s tresses beyond those listed under ?absolute m a ximum r a tings? m a y c a use perm a nent d a m- a ge to the device. this is a stress r a ting only a nd function a l oper a tion of the device a t these or a ny other conditions beyond those indic a ted in the oper a tion a l sections of this specific a tion is not implied. exposure to a bsolute m a ximum r a ting conditions for extended periods m a y a ffect device reli a bility s tor a ge temper a ture .........................................? 65 c to +150 c volt a ge on any pin with respect to ground ........................................ ? 1.0v to +7.0v m a ximum oper a ting volt a ge .......................................... 6.25v dc output current........................................................ 5.0 ma memory array 256/512 x 8 or 128/256 x 16 address decoder output buffer data register mode decode logic clock generator
3 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 note: 1. this p a r a meter is ch a r a cterized a nd is not 100% tested. note: 1. v il min a nd v ih m a x a re reference only a nd a re not tested. table 1 . pin c a p a cit a nce (1) applic a ble over recommended oper a ting r a nge from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output c a p a cit a nce (do) 5 pf v out = 0v c in input c a p a cit a nce (c s , s k, di) 5 pf v in = 0v table 2 . dc ch a r a cteristics applic a ble over recommended oper a ting r a nge from: t a = ? 40 c to +125 c, v cc = +2.7v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max unit v cc1 s upply volt a ge 2.7 5.5 v v cc2 s upply volt a ge 4.5 5.5 v i cc s upply current v cc = 5.0v read a t 1.0 mhz 0.5 2.0 ma write a t 1.0 mhz 0.5 2.0 ma i s b1 s t a ndby current v cc = 2.7v c s = 0v 6.0 10.0 a i s b2 s t a ndby current v cc = 5.0v c s = 0v 17 3 0a i il input le a k a ge v in = 0v to v cc 0.1 3 .0 a i ol output le a k a ge v in = 0v to v cc 0.1 3 .0 a v il1 (1) v ih1 (1) input low volt a ge input high volt a ge 2.7v v cc 5.5v ? 0.6 2.0 0. 8 v cc + 1 v v ol1 v oh1 output low volt a ge output high volt a ge 2.7v v cc 5.5v i ol = 2.1 ma 0.4 v i oh = ? 0.4 ma 2.4 v
4 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 note: 1. this p a r a meter is ch a r a cterized a nd is not 100% tested. table 3 . ac ch a r a cteristics applic a ble over recommended oper a ting r a nge from t a = ? 40c to + 125c, v cc = as s pecified, cl = 1 ttl g a te a nd 100 pf (unless otherwise noted). symbol parameter test condition min typ max units f s k s k clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 0 0 2 1 mhz t s kh s k high time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t s kl s k low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t c s minimum c s low time 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t c ss c s s etup time rel a tive to s k 4.5v v cc 5.5v 2.7v v cc 5.5v 50 50 ns t di s di s etup time rel a tive to s k 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t c s h c s hold time rel a tive to s k0 ns t dih di hold time rel a tive to s k 4.5v v cc 5.5v 2.7v v cc 5.5v 100 100 ns t pd1 output del a y to ?1? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t pd0 output del a y to ?0? ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 500 ns t s v c s to s t a tus v a lid ac test 4.5v v cc 5.5v 2.7v v cc 5.5v 250 250 ns t df c s to do in high imped a nce ac test c s = v il 4.5v v cc 5.5v 2.7v v cc 5.5v 100 150 ns t wp write cycle time 2.7v v cc 5.5v 0.1 3 10 ms endur a nce (1) 5.0v, 25c 1m write cycles
5 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 note: the xs in the a ddress field represent don?t c a re v a lues a nd must be clocked. functional description the at9 3 c56a/66a is a ccessed vi a a simple a nd vers a tile three-wire seri a l communi- c a tion interf a ce. device oper a tion is controlled by seven instructions issued by the host processor. a v a lid instruction st a rts with a rising edge of c s a nd consists of a s t a rt bit (logic ?1?) followed by the a ppropri a te op code a nd the desired memory address loc a tion. read (read): the re a d (read) instruction cont a ins the address code for the mem- ory loc a tion to be re a d. after the instruction a nd a ddress a re decoded, d a t a from the selected memory loc a tion is a v a il a ble a t the seri a l output pin do. output d a t a ch a nges a re synchronized with the rising edges of seri a l clock s k. it should be noted th a t a dummy bit (logic ?0?) precedes the 8 - or 16-bit d a t a output string. the at9 3 c56a/66a supports sequenti a l re a d oper a tions. the device will a utom a tic a lly increment the inter- n a l a ddress pointer a nd clock out the next memory loc a tion a s long a s chip s elect (c s ) is held high. in this c a se, the dummy bit (logic ?0?) will not be clocked out between mem- ory loc a tions, thus a llowing for a continuous stre a m of d a t a to be re a d. erase/write (ewen): to a ssure d a t a integrity, the p a rt a utom a tic a lly goes into the er a se/write dis a ble (ewd s ) st a te when power is first a pplied. an er a se/write en a ble (ewen) instruction must be executed first before a ny progr a mming instructions c a n be c a rried out. ple a se note th a t once in the er a se/write en a ble st a te, progr a mming rem a ins en a bled until a n er a se/write dis a ble (ewd s ) instruction is executed or v cc power is removed from the p a rt. erase (erase): the er a se (era s e) instruction progr a ms a ll bits in the specified memory loc a tion to the logic a l ?1? st a te. the self-timed er a se cycle st a rts once the era s e instruction a nd a ddress a re decoded. the do pin outputs the re a dy/busy st a - tus of the p a rt if c s is brought high a fter being kept low for a minimum of 250 ns (t c s ). a logic ?1? a t pin do indic a tes th a t the selected memory loc a tion h a s been er a sed, a nd the p a rt is re a dy for a nother instruction. table 4 . instruction s et for the at9 3 c56a a nd at9 3 c66a instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 8 ? a 0 a 7 ? a 0 re a ds d a t a stored in memory, a t specified a ddress ewen 1 00 11xxxxxxx 11xxxxxx write en a ble must precede a ll progr a mming modes era s e111a 8 ? a 0 a 7 ? a 0 er a ses memory loc a tion a n ? a 0 write 1 01 a 8 ? a 0 a 7 ? a 0 d 7 ? d 0 d 15 ? d 0 writes memory loc a tion a n ? a 0 eral 1 00 10xxxxxxx 10xxxxxx er a ses a ll memory loc a tions. v a lid only a t v cc = 4.5v to 5.5v. wral 1 00 01xxxxxxx 01xxxxxx d 7 ? d 0 d 15 ? d 0 writes a ll memory loc a tions. v a lid only a t v cc = 5.0v 10% a nd dis a ble register cle a red. ewd s 1 00 00xxxxxxx 00xxxxxx dis a bles a ll progr a mming instructions.
6 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 write (write): the write (write) instruction cont a ins the 8 or 16 bits of d a t a to be written into the specified memory loc a tion. the self-timed progr a mming cycle, t wp , st a rts a fter the l a st bit of d a t a is received a t seri a l d a t a input pin di. the do pin outputs the re a dy/busy st a tus of the p a rt if c s is brought high a fter being kept low for a minimum of 250 ns (t c s ). a logic ?0? a t do indic a tes th a t progr a mming is still in progress. a logic ?1? indic a tes th a t the memory loc a tion a t the specified a ddress h a s been written with the d a t a p a ttern cont a ined in the instruction a nd the p a rt is re a dy for further instructions. a re a dy/busy st a tus c a nnot be obt a ined if the c s is brought high a fter the end of the self- timed progr a mming cycle, t wp . erase all (eral): the er a se all (eral) instruction progr a ms every bit in the mem- ory a rr a y to the logic ?1? st a te a nd is prim a rily used for testing purposes. the do pin outputs the re a dy/busy st a tus of the p a rt if c s is brought high a fter being kept low for a minimum of 250 ns (t c s ). the eral instruction is v a lid only a t v cc = 5.0v 10%. write all (wral) : the write all (wral) instruction progr a ms a ll memory loc a tions with the d a t a p a tterns specified in the instruction. the do pin outputs the re a dy/busy st a tus of the p a rt if c s is brought high a fter being kept low for a minimum of 250 ns (t c s ). the wral instruction is v a lid only a t v cc = 5.0v 10%. erase/write disable (ewds): to protect a g a inst a ccident a l d a t a disturb, the er a se/write dis a ble (ewd s ) instruction dis a bles a ll progr a mming modes a nd should be executed a fter a ll progr a mming oper a tions. the oper a tion of the read instruction is independent of both the ewen a nd ewd s instructions a nd c a n be executed a t a ny time. timing diagrams figure 2. s ynchronous d a t a timing note: this is the minimum s k period. notes: 1. a 8 is a don?t c a re v a lue, but the extr a clock is required. 2. a 7 is a don?t c a re v a lue, but the extr a clock is required. 1 s (1) table 5. org a niz a tion key for timing di a gr a ms i/o at93c56a (2k) at93c66a (4k) x 8 x 16 x 8 x 16 a n a 8 (1) a 7 (2) a 8 a 7 d n d 7 d 15 d 7 d 15
7 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 figure 3. read timing figure 4. ewen timing figure 5. ewd s timing high impedance t cs cs 11 ... 00 1 sk di t cs cs t cs sk di 1 0 000 ...
8 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 figure 6. write timing figure 7. wral timing note: 1. v a lid only a t v cc = 4.5v to 5.5v. figure 8. era s e timing sk cs t cs t wp 11 a n d n 0a0d0 ... ... di do high impedance busy ready cs sk di do high impedance busy ready 1 0 0 1 ... d n t cs t wp ... d0 0 sk 1 1 ... 1 cs di a n t cs t sv t df t wp a n-1 a n-2 a0 check status standby ready busy do high impedance high impedance
9 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 figure 9. eral timing note: v a lid only a t v cc = 4.5v to 5.5v. sk cs di 1 1 00 0 do high impedance high impedance ready busy check status standby t wp t cs t sv t df
10 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 at93c56a ordering information ordering code package operation range at 9 3 c56a-10pa-5.0c at 9 3 c56a-10 s a-5.0c 8p3 8s1 automotive ( ? 40 c to 125 c) at 9 3 c56a-10pa-2.7c at 9 3 c56a-10 s a-2.7c 8p3 8s1 automotive ( ? 40 c to 125 c) package type 8p3 8 -le a d, 0. 3 00" wide, pl a stic du a l inline p a ck a ge (pdip) 8s1 8 -le a d, 0.150" wide, pl a stic gull wing s m a ll outline (jedec s oic) options ? 5.0 s t a nd a rd oper a tion (4.5v to 5.5v) ? 2.7 low volt a ge (2.7v to 5.5v)
11 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 at93c66a ordering information ordering code package operation range at 9 3 c66a-10pa-5.0c at 9 3 c66a-10 s a-5.0c 8p3 8s1 automotive ( ? 40 c to 125 c) at 9 3 c66a-10pa-2.7c at 9 3 c66a-10 s a-2.7c 8p3 8s1 automotive ( ? 40 c to 125 c) package type 8p3 8 -le a d, 0. 3 00" wide, pl a stic du a l inline p a ck a ge (pdip) 8s1 8 -le a d, 0.150" wide, pl a stic gull wing s m a ll outline (jedec s oic) options ? 5.0 s t a nd a rd oper a tion (4.5v to 5.5v) ? 2.7 low volt a ge (2.7v to 5.5v)
12 at93c56a/66a [preliminary] 3 40 3 d? s eepr?10/04 packaging information 8p3 ? pdip 2325 orchard parkway san jo s e, ca 95131 title drawing no. r rev. 8 p 3 , 8-lead, 0.300" wide body, pla s tic d u al in-line package (pdip) 01/09/02 8p3 b note s : 1. thi s drawing i s for general information only; refer to jedec drawing ms-001, variation ba, for additional information. 2. dimen s ion s a and l are mea su red with the package s eated in jedec s eating plane ga u ge gs-3. 3. d, d1 and e1 dimen s ion s do not incl u de mold fla s h or protr us ion s . mold fla s h or protr us ion s s hall not exceed 0.010 inch. 4. e and ea mea su red with the lead s con s trained to b e perpendic u lar to dat u m. 5. pointed or ro u nded lead tip s are preferred to ea s e in s ertion. 6. b 2 and b 3 maxim u m dimen s ion s do not incl u de dam b ar protr us ion s . dam b ar protr us ion s s hall not exceed 0.010 (0.25 mm). common dimen s ion s (unit of mea su re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b 3 4 plcs a ? ? 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b 2 0.045 0.060 0.070 6 b 3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 ? ? 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view
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